Adoredtv leaked a roadmap of AMD epyc Xiaolong processor, including those announced by officials, exposed and never seen. Amd Xiaolong has developed three generations of products, all of which are unified SP3 packaging interfaces, and the next new interface is not only the SP5 that has been exposed for many times, but also an SP6 that will be added synchronously, as is the case with zen4 architecture and zen5 architecture**
Zen4 architecture and SP5 interface have two series of products:
One is "Genoa" (Genoa), with up to 96 zen4 cores and 192 threads, and the power consumption range is 200-400W**
The second is "Bergamo", with 128 zen4c cores and 256 threads at most, and the power consumption range is 320-400w**
They all support single and dual configurations, 12 channel ddr5 memory, 160 PCIe 5.0 buses, 12 PCIe 3.0 buses and 64 CXL v1 1 + high speed interconnect bus**
In fact, Genoa also has a derivative version of "genoa-x", which is similar to the current milan-x and also adds 3D v-cache stack cache**
However, so far, we are still uncertain about the specific difference between zen4 and zen4c, which may be more optimized for cloud computing.
*The products of zen4 architecture and SP6 interface have no clear code. The difference is that they only support single channel configuration *. Compared with SP5, they have higher computing density and energy efficiency, and are optimized for edge computing and telecommunications infrastructure.
It has up to 32 zen4 cores or 64 zen4c cores, and the power consumption range is reduced to 70-225w. At the same time, it is reduced to 6-channel ddr5, 96 PCIe 5.0, 8 PCIe 3.0 and 48 CXL 1.1 +, that is, one-third to half of the specifications are cut
*The product code of zen5 architecture is "Turin) *. There are also two interface versions of SP5 and SP6, but the specific specifications are not clear for the time being. It is expected that there will be up to 256 core 512 threads and 12 channel ddr5-6000.
*The next generation of product code "Venice" (Venice) *, is supposed to use zen6 architecture, but I don't know whether the process will continue to 5nm or upgrade to 3nm?
